The present invention relates generally to structures and methods for strengthening/supporting dielectric membranes which extend over the over cavities in integrated circuit devices, and more particularly to use of various sizes, shapes, and relative locations of etchant openings in the dielectric membranes through which to introduce etchant for etching the cavities.
This invention is closely related to the assignee's pending application “INFRARED SENSOR STRUCTURE AND METHOD” by Walter B. Meinel and Kalin V. Lazarov, Ser. No. 12/380,316, filed Feb. 26, 2009, and incorporated herein by reference.
Integrated semiconductor sensors can make use of SiO2 membrane structures which extend from, or “overhang” from, a silicon base or the like, for example, to cover a cavity etched into the silicon base. Such membrane structures tend to be fragile and therefore susceptible to damage during assembly operations which occur after formation of the membrane structures. For example, to achieve maximum sensitivity, the cavity openings covered by the SiO2 membrane in the infrared sensors described in the above mentioned Meinel et al. application should be as large as possible, but unfortunately this causes. the SiO2 membrane to be more fragile.
The closest prior art is believed to include the article “Investigation Of Thermopile Using CMOS Compatible Process and Front-Side Si Bulk Etching” by Chen-Hsun-Du and Chengkuo Lee, Proceedings of SPIE Vol. 4176 (2000), pp. 168-178, incorporated herein by reference. Infrared thermopile sensor physics and measurement of IR radiation using thermopiles are described in detail in this reference. Prior Art FIG. 1 herein shows the CMOS-processing-compatible IR sensor integrated circuit chip in FIG. 1 of the foregoing article. “Prior Art” FIG. 1 herein is similar to drawing, and Prior FIG. 1B herein shows the top perspective view of the same IR sensor integrated circuit chip illustrated in FIG. 2 of the foregoing article.
Referring to Prior Art FIG. 1A herein, the IR sensor chip includes a silicon substrate 2 having a CMOS-processing-compatible dielectric (SiO2) stack 3 thereon including a number of distinct sub-layers. A N-type polysilicon (polycrystalline silicon) trace 11 and an aluminum trace M1 in dielectric stack 3 form a first “thermopile junction” where one end of the polysilicon trace and one end of the aluminum trace are connected. Additional oxide layers and additional metal traces also may be included in dielectric stack 3. An oxide passivation layer 12A is formed on top of dielectric stack 3, and a nitride passivation layer 12B is formed on oxide passivation layer 12A. A number of silicon etchant openings 24 extend through nitride passivation layer 12 and dielectric stack 3 to the top surface of silicon substrate 2 and are used to etch a cavity 4 in silicon substrate 2 underneath the portion of dielectric stack 3 in which the thermopile is formed, to thermally isolate it from silicon substrate 2.
Prior Art FIG. 1A is taken along section line 1A-1A of Prior Art FIG. 1B, which is essentially similar to FIG. 2 of the above mentioned Du and Lee reference. Cavity 4 is etched underneath SiO2 stack 3 by means of silicon etchant introduced through the various etchant openings 24, which are relatively large and irregular. FIG. 1B shows various metal-polysilicon strips MP1 each of which includes an aluminum strip M1 and a polysilicon strip 11 which makes electrical contact to the aluminum strip M1 as shown in FIG. 1B. The metal strips M1 run parallel to the polysilicon strips 11 and, except for the electrical contact between them as shown in FIG. 1A, are separated from polysilicon strips 11 by a sublayer of SiO2 stack 3. Although not shown in FIG. 1A, the dielectric material directly above metal strips M1 actually has corresponding steps which are indicated by reference numerals MP2 in FIG. 1B. The relatively large etchant openings 24 and their various angular shapes cause the “floating” membrane consisting of the various metal-polysilicon strips MP1 and the central section 3A of SiO2 stack 3 supported by metal-polysilicon strips MP1 to be very fragile. Such fragility ordinarily results in an unacceptably large number of device failures during subsequent wafer fabrication, subsequent packaging, and ultimate utilization of the IR sensor of FIGS. 1A and 1B.
A second thermopile junction (not shown) is also formed in dielectric stack 3 directly over a silicon substrate 2 and is not thermally isolated from silicon substrate 2 and therefore is at the same temperature as silicon substrate 2. The first and second thermopile junctions are connected in series and form a single “thermopile”. The various silicon etchant openings 24 are formed in regions in which there are no polysilicon or aluminum traces, as shown in the dark areas in FIG. 2 of the Du and Lee article.
Incoming IR radiation indicated by arrows 5 in Prior Art FIG. 1 impinges on the “front side” or “active surface” of the IR sensor chip. (The “back side” of the chip is the bottom surface of silicon substrate 2 as it appears in Prior Art FIG. 1.) The incoming IR radiation 5 causes the temperature of the thermopile junction supported on the “floating” portion of dielectric membrane 3 located directly above cavity 4 to be greater than the temperature of the second thermopile junction (not shown) in dielectric membrane 3 which is not insulated by cavity 4.
When performing silicon etching by introducing silicon etchant through openings in a dielectric layer of a semiconductor device wherein the etching undercuts the dielectric layer to provide a cavity underneath the dielectric layer, the resulting undercut dielectric membrane is very fragile and can be damaged during further processing of the semiconductor device. It also is desirable to be able to prevent dirt or fluids from entering into the cavity through openings. During subsequent wafer processing, a jet of water typically is directed onto the wafer surface to clean it during wafer sawing operations. This causes high stress in the SiO2 membrane over the etched cavity. The high stress may exceed the SiO2 membrane strength, and cavitation which occurs during the wafer sawing may further amplify the stresses therein. Cracks may propagate from high stress points in the SiO2 membrane across portions thereof supporting conductors and/or other circuit elements fabricated within the SiO2 membrane. Such cracks may result in integrated circuit device failure or unreliable device operation.
Furthermore, the performance of circuit elements fabricated within the dielectric membrane depends on having only air, which has a very low dielectric constant, underneath the dielectric membrane.
It would be highly desirable to provide integrated circuit devices which include fragile dielectric membranes that extend over cavities and which are more economical and more robust than those known in the prior art.
It is well-known that the upper limit of the operating frequency of an integrated circuit is often determined by the amount of parasitic capacitance associated with circuit elements such as resistors and/or capacitors and/or inductors therein. It would be very beneficial to be able to substantially lower such parasitic capacitance.
It would be highly desirable to provide integrated circuit devices which include fragile “cantilevered” dielectric membranes and which are more economical and more robust than those known in the prior art. It also would be highly desirable to provide robust integrated circuits that are operable at higher RF frequencies than previously have been economically achievable.
There is an unmet need for integrated circuit devices which include fragile “cantilevered” dielectric membranes and which are more robust than those known in the prior art.
There also is an unmet need for an IR radiation sensor which includes a fragile “cantilevered” dielectric membrane and which is more robust than those known in the prior art.
There also is an unmet need for a CMOS-processing-compatible IR radiation sensor chip which is substantially more robust than those of the prior art.
There also is an unmet need for an improved method of fabricating an IR radiation sensor.
There also is an unmet need for a robust, economical integrated circuit that is operable at higher RF frequencies than have been previously achievable for similar integrated circuits.
There also is an unmet need for a way of providing a circuit component having reduced parasitic capacitance in an integrated circuit.
There also is an unmet need for a way of providing a resistor and/or a capacitor and/or an inductor having reduced parasitic capacitance in an integrated circuit.